Technology Assessment Methodology for Complementary Logic Applications Based on Energy-Delay Optimization
- Authors
- Wei, Lan; Oh, Saeroonter; Wong, H. -S. Philip
- Issue Date
- Aug-2011
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Keywords
- Complementary metal-oxide-semiconductor (CMOS); delay; energy; technology assessment
- Citation
- IEEE TRANSACTIONS ON ELECTRON DEVICES, v.58, no.8, pp.2430 - 2439
- Indexed
- SCIE
SCOPUS
- Journal Title
- IEEE TRANSACTIONS ON ELECTRON DEVICES
- Volume
- 58
- Number
- 8
- Start Page
- 2430
- End Page
- 2439
- URI
- https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/37263
- DOI
- 10.1109/TED.2011.2157349
- ISSN
- 0018-9383
- Abstract
- Historically, the OFF-state current I-off and the supply voltage V-dd are specified as technology targets for Si metal-oxide-semiconductor field-effect transistors (MOSFETs) at each technology node. Emerging device technologies such as III-V transistors, carbon-nanotube FETs (CNFETs), and tunneling FETs (TFETs) are often targeted to outperform Si MOSFETs at the same I-off and V-dd values. However, the conclusions from the conventional methodology are limited for advanced technology and diversified applications, when Dennard scaling is inefficient and different device structures are invented. We present a new device-technology assessment methodology based on energy-delay optimization, which takes into consideration key circuit-level information, such as logic depth, activity factors, and fanout (FO). Our methodology starts from device I-V and C-V characteristics and treat I-off and V-dd as "free variables." Together with device and supply-voltage variations, we obtain a corresponding and different optimal set of I-off and V-dd and optimal energy-delay for each emerging device. We show that today's best available III-V transistors and CNFETs can outperform the best Si FETs by 1.5-2 and 2-3.5 times in terms of energy efficiency, respectively. Projected into the 10-nm-gate-length regime, III-V-on-insulator, CNFETs, and TFETs are 1.25, 2-3, and 5-10 times better than the International Technology Roadmap for Semiconductors target, for FO1 delays of 0.3, 0.1, and 1 ns, respectively.
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