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Viability Study of All-III-V SRAM for Beyond-22-nm Logic Circuits
- Authors
- Oh, Saeroonter; Wong, H. -S. Philip
- Issue Date
- Jul-2011
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Keywords
- Alternative channel FET; compact model; III-V; logic circuits; SPICE simulation; SRAM
- Citation
- IEEE ELECTRON DEVICE LETTERS, v.32, no.7, pp.877 - 879
- Indexed
- SCIE
SCOPUS
- Journal Title
- IEEE ELECTRON DEVICE LETTERS
- Volume
- 32
- Number
- 7
- Start Page
- 877
- End Page
- 879
- ISSN
- 0741-3106
- Abstract
- Aphysics-based compact model for III-V FETs is developed for logic circuit applications. The model is applied to study sub-22-nm technology 6T-SRAM cells with InGaAs MOSFETs. The pull-down and pass gate combination is optimized for maximum cell stability. The drawbacks of having a weak III-V PMOS as the pull-up device in a SRAM cell are investigated. In this letter, we propose a minimum requirement for PMOS strength for all-III-V SRAM to be viable in a logic chip. Also, by assuming a high-performance PMOS, we observe a 26% higher static current noise margin and a two times faster write speed compared to conventional SRAM.
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Related Researcher
- OH, SAE ROON TER
- ERICA 공학대학 (SCHOOL OF ELECTRICAL ENGINEERING)