Experimental via characterization for the signal integrity verification of discontinuous interconnect line
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kim, Hyewon | - |
dc.contributor.author | Kim, Dongchul | - |
dc.contributor.author | Eo, Yungseon | - |
dc.date.accessioned | 2021-06-23T14:36:54Z | - |
dc.date.available | 2021-06-23T14:36:54Z | - |
dc.date.created | 2021-01-22 | - |
dc.date.issued | 2010-11 | - |
dc.identifier.issn | 0000-0000 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/40494 | - |
dc.description.abstract | Interconnect lines with inter-layer vias are experimentally characterized by using high-frequency S-parameter measurements. Test patterns are designed and fabricated using a package process and measured using Vector Network Analyzer (VNA) up to 25 GHz. Then, by modeling a via as a circuit, its model parameters are determined. It is shown that the circuit model has excellent agreement with the measured S-parameters. The circuit performance of the lines with inter-layer vias is evaluated by using the developed circuit model. Thereby, it is shown that via may have a substantially deteriorative effect on the signal integrity of high-speed integrated circuits. ©2010 IEEE. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | IEEE | - |
dc.title | Experimental via characterization for the signal integrity verification of discontinuous interconnect line | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Eo, Yungseon | - |
dc.identifier.doi | 10.1109/SOCDC.2010.5682933 | - |
dc.identifier.scopusid | 2-s2.0-79851504898 | - |
dc.identifier.bibliographicCitation | 2010 International SoC Design Conference, ISOCC 2010, pp.213 - 216 | - |
dc.relation.isPartOf | 2010 International SoC Design Conference, ISOCC 2010 | - |
dc.citation.title | 2010 International SoC Design Conference, ISOCC 2010 | - |
dc.citation.startPage | 213 | - |
dc.citation.endPage | 216 | - |
dc.type.rims | ART | - |
dc.type.docType | Conference Paper | - |
dc.description.journalClass | 3 | - |
dc.description.isOpenAccess | N | - |
dc.description.journalRegisteredClass | other | - |
dc.subject.keywordPlus | Circuit models | - |
dc.subject.keywordPlus | Circuit performance | - |
dc.subject.keywordPlus | Eye-diagram | - |
dc.subject.keywordPlus | High frequency HF | - |
dc.subject.keywordPlus | High-speed integrated circuits | - |
dc.subject.keywordPlus | Interconnect lines | - |
dc.subject.keywordPlus | Model parameters | - |
dc.subject.keywordPlus | S -parameters | - |
dc.subject.keywordPlus | S-parameter | - |
dc.subject.keywordPlus | S-Parameter measurements | - |
dc.subject.keywordPlus | Signal Integrity | - |
dc.subject.keywordPlus | Test Pattern | - |
dc.subject.keywordPlus | Vector network analyzers | - |
dc.subject.keywordPlus | Via | - |
dc.subject.keywordPlus | Electric network analysis | - |
dc.subject.keywordPlus | Microprocessor chips | - |
dc.subject.keywordPlus | Scattering parameters | - |
dc.subject.keywordPlus | Electric network analyzers | - |
dc.subject.keywordAuthor | Circuit model | - |
dc.subject.keywordAuthor | Eye-diagram | - |
dc.subject.keywordAuthor | S-parameter | - |
dc.subject.keywordAuthor | Via | - |
dc.identifier.url | https://ieeexplore.ieee.org/document/5682933 | - |
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