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Experimental via characterization for the signal integrity verification of discontinuous interconnect line

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dc.contributor.authorKim, Hyewon-
dc.contributor.authorKim, Dongchul-
dc.contributor.authorEo, Yungseon-
dc.date.accessioned2021-06-23T14:36:54Z-
dc.date.available2021-06-23T14:36:54Z-
dc.date.created2021-01-22-
dc.date.issued2010-11-
dc.identifier.issn0000-0000-
dc.identifier.urihttps://scholarworks.bwise.kr/erica/handle/2021.sw.erica/40494-
dc.description.abstractInterconnect lines with inter-layer vias are experimentally characterized by using high-frequency S-parameter measurements. Test patterns are designed and fabricated using a package process and measured using Vector Network Analyzer (VNA) up to 25 GHz. Then, by modeling a via as a circuit, its model parameters are determined. It is shown that the circuit model has excellent agreement with the measured S-parameters. The circuit performance of the lines with inter-layer vias is evaluated by using the developed circuit model. Thereby, it is shown that via may have a substantially deteriorative effect on the signal integrity of high-speed integrated circuits. ©2010 IEEE.-
dc.language영어-
dc.language.isoen-
dc.publisherIEEE-
dc.titleExperimental via characterization for the signal integrity verification of discontinuous interconnect line-
dc.typeArticle-
dc.contributor.affiliatedAuthorEo, Yungseon-
dc.identifier.doi10.1109/SOCDC.2010.5682933-
dc.identifier.scopusid2-s2.0-79851504898-
dc.identifier.bibliographicCitation2010 International SoC Design Conference, ISOCC 2010, pp.213 - 216-
dc.relation.isPartOf2010 International SoC Design Conference, ISOCC 2010-
dc.citation.title2010 International SoC Design Conference, ISOCC 2010-
dc.citation.startPage213-
dc.citation.endPage216-
dc.type.rimsART-
dc.type.docTypeConference Paper-
dc.description.journalClass3-
dc.description.isOpenAccessN-
dc.description.journalRegisteredClassother-
dc.subject.keywordPlusCircuit models-
dc.subject.keywordPlusCircuit performance-
dc.subject.keywordPlusEye-diagram-
dc.subject.keywordPlusHigh frequency HF-
dc.subject.keywordPlusHigh-speed integrated circuits-
dc.subject.keywordPlusInterconnect lines-
dc.subject.keywordPlusModel parameters-
dc.subject.keywordPlusS -parameters-
dc.subject.keywordPlusS-parameter-
dc.subject.keywordPlusS-Parameter measurements-
dc.subject.keywordPlusSignal Integrity-
dc.subject.keywordPlusTest Pattern-
dc.subject.keywordPlusVector network analyzers-
dc.subject.keywordPlusVia-
dc.subject.keywordPlusElectric network analysis-
dc.subject.keywordPlusMicroprocessor chips-
dc.subject.keywordPlusScattering parameters-
dc.subject.keywordPlusElectric network analyzers-
dc.subject.keywordAuthorCircuit model-
dc.subject.keywordAuthorEye-diagram-
dc.subject.keywordAuthorS-parameter-
dc.subject.keywordAuthorVia-
dc.identifier.urlhttps://ieeexplore.ieee.org/document/5682933-
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