Line Edge Roughness Reduction Using Resist Reflow Process for 22 nm Node Extreme Ultraviolet Lithography

Abstract

Extreme ultraviolet lithography (EUVL) has been developed and studied for a sub-22 nm semiconductor device. It is difficult to obtain a smooth sub-22 nm pattern because line edge roughness (LER) and linewidth roughness (LWR) cannot be controlled well. According to the 2008 ITRS roadmap, LER has to be below 1.3 nm to achieve a 22 nm node for EUVL. In our previous work, the resist reflow process (RRP), in which the resist is baked above the glass transition temperature (T-g), was very helpful for reducing LER and LWR for EUVL. LER and LWR could be decreased from similar to 6 to similar to 1 nm. As RRP time progresses, however, the critical dimension could become wider because the developed resist can flow more easily when the temperature is above T-g. Therefore, another method is suggested to solve this problem. The developed resist, which is intentionally designed with a 1 : 3 line and space (L/S) (11 : 33 nm) pattern, is baked above T-g. As a result, LER and LWR can be smoothed by RRP and we could achieve a 22 nm 1 : 1 L/S pattern with a small LER. (C) 2010 The Japan Society of Applied Physics