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Signal integrity verification of coplanar structures for shielded on-chip interconnect lines
- Authors
- Khan, Zafar; Kim, Hyewon; Eo, Yungseon
- Issue Date
- Nov-2009
- Publisher
- IEEE
- Keywords
- On chip interconnect; Bit rates; Interconnect lines; Area savings; Electric lines; Signal Integrity; Programmable logic controllers; Ground signal grounds; On chips; Quality assurance; Transmission line; Ground structure; Coplanar structure; Coplanar wave
- Citation
- 2009 International SoC Design Conference
- Indexed
- OTHER
- Journal Title
- 2009 International SoC Design Conference
- Abstract
- This paper analyses and compares two Coplanar Structures to be employed as shielded structures for on-chip critical interconnect lines such as clock. It is believed that at lower bit rates, on-chip area overhead caused by the Ground-Signal-Ground structure can be mitigated by a coplanar Power-Signal-Ground structure, if the performance of the two is not much different. However at higher bit rates, in addition to area saving, the later structure is shown to be better performance wise. ©2009 IEEE.
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Related Researcher
- EO, YUNG SEON
- ERICA 공학대학 (SCHOOL OF ELECTRICAL ENGINEERING)