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Simulated Annealing을 이용한 FPGA 배치에서의 cooling 계획Cooling schedule for FPGA Placement using Simulated Annealing
- Other Titles
- Cooling schedule for FPGA Placement using Simulated Annealing
- Authors
- 신현철
- Issue Date
- Nov-2009
- Publisher
- 대한전자공학회
- Citation
- 대한전자공학회 추계학술대회, v. , no. , pp.1 - 2
- Journal Title
- 대한전자공학회 추계학술대회
- Start Page
- 1
- End Page
- 2
- Abstract
- In this paper, we propose a new cooling schedule for placement of Field Programmable Gate Array (FPGA) by using Simulated Annealing. By using the proposed cooling schedule, we obtain improved results, when compared to those of Versatile Place and Route (VPR). Experiment results shows that cost and move number were reduced by 0.3%, 22.8% respectively.
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