Highly Compact Interconnect Test Patterns for Crosstalk and Static Faults

Abstract

The effect of crosstalk-induced errors becomes more significant in high-performance circuits and systems. In this paper, compact crosstalk test patterns are introduced for a system-on-a-chip and board level interconnects considering physically effective aggressors. By being able to target multiple victim lines, 6n, where n is the number of nets patterns are drastically reduced to a constant number 6D, where D indicates the effective distance among interconnect nets. The test quality for static and crosstalk faults are completely preserved with 6D patterns.