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DFD를 위한 효율적인 콤플렉스 셀 설계Efficient Complex Cell Design for Design for Debug
- Other Titles
- Efficient Complex Cell Design for Design for Debug
- Authors
- 신현철
- Issue Date
- Nov-2008
- Publisher
- 대한전자공학회
- Citation
- 2008 SoC 추계학술대회
- Journal Title
- 2008 SoC 추계학술대회
- Abstract
- In this paper, we propose complex gate type structures, for design for debug and repair. When an error is found on a semiconductor chip, we want to fix the error by using the spare cells. Our complex gates based spare cells use 55% less NMOSs and PMOSs on the average, when compared to standard cell NAND gate structures, for ISCAS85 benchmark circuits.
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