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Low-cost scan test for IEEE-1500-Based SoC
- Authors
- Yi, Hyunbean; Song, Jaehoon; Park, Sungju
- Issue Date
- May-2008
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Keywords
- delay test; design-for-testability (DtT); IEEE 1500; reduced pin-count test (RPCT); system-on-a-chip (SoC)
- Citation
- IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, v.57, no.5, pp 1071 - 1078
- Pages
- 8
- Indexed
- SCIE
SCOPUS
- Journal Title
- IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT
- Volume
- 57
- Number
- 5
- Start Page
- 1071
- End Page
- 1078
- ISSN
- 0018-9456
1557-9662
- Abstract
- In this paper, a reduced-pin-count-testing technique is presented to control the IEEE-1500 wrapper through the IEEE-1149.1 TAP for scan delay test. By using only the IEEE1149.1 TAP control pins as test-access pins and by embedding an on-chip test clock generator, low-cost automated test equipment (ATE) can be efficiently utilized to reduce testing costs. Experiments show the effectiveness of our technique in utilizing the ATE channels and scan delay testing.
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Collections - COLLEGE OF COMPUTING > SCHOOL OF COMPUTER SCIENCE > 1. Journal Articles
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