A high performance motion vector processor IP design for H.264/AVC
- Authors
- Yoo, Kiwon; Park, Seungho; Ko, Hyunsuk; Sohn, Kwanghoon
- Issue Date
- Apr-2008
- Publisher
- IEEE
- Citation
- 2008 12th IEEE International Symposium on Consumer Electronics ( ISCE2008), pp.319 - 322
- Indexed
- SCIE
SCOPUS
- Journal Title
- 2008 12th IEEE International Symposium on Consumer Electronics ( ISCE2008)
- Start Page
- 319
- End Page
- 322
- URI
- https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/43058
- DOI
- 10.1109/ISCE.2008.4559504
- Abstract
- In this paper, the world's first hardware design of the motion vector processor of H.264/AVC and its FPGA implementation are presented. It aims at a low-cost high-throughput design for HD1080 (1920 x 1088) at 60 frames per second (fps) in High Profile (HP) H.264/AVC codec with Level 4.2. For this, deterministic processing loops control scheme and a novel 4 x 4 processing order substituting for the conventional double-Z one are presented to attain a high-throughput design. In addition, for maximizing hardware utilization and getting a low-cost design, two processing elements dedicated to motion vector derivation are presented. The proposed design was realized with 41 K logic gates and 4,608 bits SRAM at 266 MHz and was completely conformed for Allegro compliance bitstreams on an FPGA platform.
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