32 nm 1:1 line and space patterning by resist reflow process

Abstract

Making a sub-32 nm line and space pattern is the most important issue in semiconductor process. Specially, it is important to make line and space pattern when the device type is NAND flash memory because the unit cell is mostly composed of line and space pattern. Double patterning method is regarded as the most promising technology for sub-32 nm half-pitch node. However, double patterning method is expensive for the production and heavy data split is required. In order to make cheaper and easier patterning, we suggest a resist reflow process (RRP) method for 32 nm 1:1 line and space pattern. It is easier to make 1:3 pitch than 1:1 pitch line and space in terms of aerial image, and RRP can make 1:3 pitch aerial image to 1:1 resist image. We used home-made RRP simulation based on Navier-Stokes equation including surface tension effect. Solid-E is used for optical simulation, and e-beam lithography is used for the experiment to check the concept.