천이 지연 고장 테스트를 위한 IEEE 1500 래퍼 셀 설계

Abstract

As the integration density of System on Chips (SoCs) and the operating speed become increasingly fast, it is crucial to test delay. In order to detect transition delay fault, the test responses must be captured in a system clock cycle after applying sequential test pattern. This paper introduces an IEEE 1500 wrapper cell architecture and IEEE 1149.1 TAP controller to wrapper serial port interface logic, and propose a transition delay fault test. Proposed method can simultaneously test of transition delay fault of IEEE 1500 wrapped cores using different core clocks, has low area overhead, and reduces test time.