천이 지연 고장 테스트를 위한 IEEE 1500 래퍼 셀 설계Design of IEEE 1500 Wrapper Cell For Transition Delay Fault Test
- Other Titles
- Design of IEEE 1500 Wrapper Cell For Transition Delay Fault Test
- Authors
- 김기태; 한주희; 황두찬; 박성주
- Issue Date
- Nov-2006
- Publisher
- 대한전자공학회
- Citation
- 2006년 대한전자공학회 추계종합학술대회 논문집(II), v.29, no.2, pp.391 - 394
- Indexed
- OTHER
- Journal Title
- 2006년 대한전자공학회 추계종합학술대회 논문집(II)
- Volume
- 29
- Number
- 2
- Start Page
- 391
- End Page
- 394
- URI
- https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/44525
- Abstract
- As the integration density of System on Chips (SoCs) and the operating speed become increasingly fast, it is crucial to test delay. In order to detect transition delay fault, the test responses must be captured in a system clock cycle after applying sequential test pattern. This paper introduces an IEEE 1500 wrapper cell architecture and IEEE 1149.1 TAP controller to wrapper serial port interface logic, and propose a transition delay fault test. Proposed method can simultaneously test of transition delay fault of IEEE 1500 wrapped cores using different core clocks, has low area overhead, and reduces test time.
- Files in This Item
-
Go to Link
- Appears in
Collections - COLLEGE OF COMPUTING > SCHOOL OF COMPUTER SCIENCE > 1. Journal Articles
![qrcode](https://api.qrserver.com/v1/create-qr-code/?size=55x55&data=https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/44525)
Items in ScholarWorks are protected by copyright, with all rights reserved, unless otherwise indicated.