Layout Design Optimization for Manufacturability by Using 2D Compaction

Abstract

Layout modification techniques have been developed for yield and realiability enhancement. As CMOS manufacturing technology is scaled down to 90 nm and below, designers need to consider complicated physical effects, and thus the number of design rules to maintain is rapidly increasing. Important features of layout optimization include forbidden pitch, end-of-wire extension, and redundant via insertion. To complete the targeted layout optimization within minimal area, we use two-dimensional layout compaction techniques. When the layout is given in geometric from, we extract its symbolic layout by identifying transistors, vias, and wires, and then use compaction to optimize the layout. Experimental results show that the suggested techniques are promising in optimizing layout for manufacturability.