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Interconnect delay fault test on boards and SoCs with multiple clock domains

Authors
Yi, HyunbeanSong, JaehoonPark, Sungju
Issue Date
Oct-2006
Publisher
Institute of Electrical and Electronics Engineers Inc.
Citation
Proceedings - International Test Conference, pp.1 - 7
Indexed
SCIE
SCOPUS
Journal Title
Proceedings - International Test Conference
Start Page
1
End Page
7
URI
https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/45334
DOI
10.1109/TEST.2006.297632
ISSN
1089-3539
Abstract
This paper introduces an efficient interconnect delay fault test (IDFT) controller on boards and SoCs with IEEE 1149.1 and IEEE 1500 wrappers. By capturing the transition signals launched during one system clock, interconnect delay faults operated by different system clocks can be effectively tested with our technique. The IDFT controller proposed does not require any modification on boundary scan cells, instead very simple logic needs to be plugged around the TAP controller. Complete compatibility with the IEEE 1149.1 and IEEE 1500 standards is preserved and the superiority of this approach is verified through design experiments. © 2006 IEEE.
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