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Parallel CRC logic optimization algorithm for high speed communication systems
- Authors
- Yi, Hyunbean; Song, Jaehoon; Park, Sungju; Park, Changwon
- Issue Date
- Nov-2006
- Publisher
- IEEE
- Citation
- 2006 IEEE Singapore International Conference on Communication Systems, ICCS 2006, pp.1 - 5
- Indexed
- SCIE
SCOPUS
- Journal Title
- 2006 IEEE Singapore International Conference on Communication Systems, ICCS 2006
- Start Page
- 1
- End Page
- 5
- Abstract
- This paper presents a new optimization algorithm for designing parallel Cyclic Redundancy Check (CRC) circuits widely adopted to detect burst errors in high-speed communications. Our heuristic algorithm is focused on minimizing the logic level and finding XOR terms shared as many as possible. An Ethernet 32-bit CRC generator, which was designed and mapped to FPGA and a standard cell library, shows the superiority of our approach in reducing the delay and area overhead. © 2006 IEEE.
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