Detailed Information

Cited 0 time in webofscience Cited 0 time in scopus
Metadata Downloads

Fast and accurate quasi-three-dimensional capacitance determination of multilayer VLSI interconnects

Full metadata record
DC Field Value Language
dc.contributor.authorJin, Woojin-
dc.contributor.authorEo, Yungseon-
dc.contributor.authorEisenstadt, WR-
dc.contributor.authorShim, Jong In-
dc.date.accessioned2021-06-24T01:05:15Z-
dc.date.available2021-06-24T01:05:15Z-
dc.date.issued2001-06-
dc.identifier.issn1063-8210-
dc.identifier.issn1557-9999-
dc.identifier.urihttps://scholarworks.bwise.kr/erica/handle/2021.sw.erica/46901-
dc.description.abstractA new fast and accurate capacitance determination methodology for intricate multilayer VLSI interconnects is presented, Since a multilayer interconnect structure is too complicated to be directly tractable, it is simplified by investigating charge distributions within the system, The quasi-three-dimensional (3-D) capacitances of the structure are then determined by combining a set of solid-ground-based two-dimensional (2-D) capacitances and shielding effects that can be independently calculated from the simplified structure, The shielding effects due to the neighboring lines of a line can be analytically determined from the given layout dimensions, The solid-ground-based 2-D capacitances can also be quickly computed from the simplified structure. Thus, the proposed capacitance determination methodology is much more cost-efficient than conventional 3-D-based methods. It is shown that the calculated quasi-3-D capacitances have excellent agreement with 3-D held-solver-based results within 5% error.-
dc.format.extent11-
dc.language영어-
dc.language.isoENG-
dc.publisherInstitute of Electrical and Electronics Engineers-
dc.titleFast and accurate quasi-three-dimensional capacitance determination of multilayer VLSI interconnects-
dc.typeArticle-
dc.publisher.location미국-
dc.identifier.doi10.1109/92.929579-
dc.identifier.scopusid2-s2.0-0035361132-
dc.identifier.wosid000169453100004-
dc.identifier.bibliographicCitationIEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.9, no.3, pp 450 - 460-
dc.citation.titleIEEE Transactions on Very Large Scale Integration (VLSI) Systems-
dc.citation.volume9-
dc.citation.number3-
dc.citation.startPage450-
dc.citation.endPage460-
dc.type.docTypeArticle-
dc.description.isOpenAccessN-
dc.description.journalRegisteredClassscie-
dc.description.journalRegisteredClassscopus-
dc.relation.journalResearchAreaComputer Science-
dc.relation.journalResearchAreaEngineering-
dc.relation.journalWebOfScienceCategoryComputer Science, Hardware & Architecture-
dc.relation.journalWebOfScienceCategoryEngineering, Electrical & Electronic-
dc.subject.keywordPlus3-DIMENSIONAL CAPACITANCE-
dc.subject.keywordPlusMICROPROCESSOR-
dc.subject.keywordPlusEXTRACTION-
dc.subject.keywordPlusDESIGN-
dc.subject.keywordPlusMODELS-
dc.subject.keywordAuthorcrosstalk-
dc.subject.keywordAuthorinterconnect capacitance-
dc.subject.keywordAuthormultilayer-
dc.subject.keywordAuthorshielding effect-
dc.subject.keywordAuthorsignal delay-
dc.subject.keywordAuthorVLSI interconnects-
dc.identifier.urlhttps://ieeexplore.ieee.org/document/929579-
Files in This Item
Go to Link
Appears in
Collections
COLLEGE OF SCIENCE AND CONVERGENCE TECHNOLOGY > DEPARTMENT OF PHOTONICS AND NANOELECTRONICS > 1. Journal Articles
COLLEGE OF ENGINEERING SCIENCES > SCHOOL OF ELECTRICAL ENGINEERING > 1. Journal Articles

qrcode

Items in ScholarWorks are protected by copyright, with all rights reserved, unless otherwise indicated.

Related Researcher

Researcher EO, YUNG SEON photo

EO, YUNG SEON
ERICA 공학대학 (SCHOOL OF ELECTRICAL ENGINEERING)
Read more

Altmetrics

Total Views & Downloads

BROWSE