Fast and accurate quasi-three-dimensional capacitance determination of multilayer VLSI interconnects
DC Field | Value | Language |
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dc.contributor.author | Jin, Woojin | - |
dc.contributor.author | Eo, Yungseon | - |
dc.contributor.author | Eisenstadt, WR | - |
dc.contributor.author | Shim, Jong In | - |
dc.date.accessioned | 2021-06-24T01:05:15Z | - |
dc.date.available | 2021-06-24T01:05:15Z | - |
dc.date.issued | 2001-06 | - |
dc.identifier.issn | 1063-8210 | - |
dc.identifier.issn | 1557-9999 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/46901 | - |
dc.description.abstract | A new fast and accurate capacitance determination methodology for intricate multilayer VLSI interconnects is presented, Since a multilayer interconnect structure is too complicated to be directly tractable, it is simplified by investigating charge distributions within the system, The quasi-three-dimensional (3-D) capacitances of the structure are then determined by combining a set of solid-ground-based two-dimensional (2-D) capacitances and shielding effects that can be independently calculated from the simplified structure, The shielding effects due to the neighboring lines of a line can be analytically determined from the given layout dimensions, The solid-ground-based 2-D capacitances can also be quickly computed from the simplified structure. Thus, the proposed capacitance determination methodology is much more cost-efficient than conventional 3-D-based methods. It is shown that the calculated quasi-3-D capacitances have excellent agreement with 3-D held-solver-based results within 5% error. | - |
dc.format.extent | 11 | - |
dc.language | 영어 | - |
dc.language.iso | ENG | - |
dc.publisher | Institute of Electrical and Electronics Engineers | - |
dc.title | Fast and accurate quasi-three-dimensional capacitance determination of multilayer VLSI interconnects | - |
dc.type | Article | - |
dc.publisher.location | 미국 | - |
dc.identifier.doi | 10.1109/92.929579 | - |
dc.identifier.scopusid | 2-s2.0-0035361132 | - |
dc.identifier.wosid | 000169453100004 | - |
dc.identifier.bibliographicCitation | IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.9, no.3, pp 450 - 460 | - |
dc.citation.title | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | - |
dc.citation.volume | 9 | - |
dc.citation.number | 3 | - |
dc.citation.startPage | 450 | - |
dc.citation.endPage | 460 | - |
dc.type.docType | Article | - |
dc.description.isOpenAccess | N | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Computer Science | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Hardware & Architecture | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.subject.keywordPlus | 3-DIMENSIONAL CAPACITANCE | - |
dc.subject.keywordPlus | MICROPROCESSOR | - |
dc.subject.keywordPlus | EXTRACTION | - |
dc.subject.keywordPlus | DESIGN | - |
dc.subject.keywordPlus | MODELS | - |
dc.subject.keywordAuthor | crosstalk | - |
dc.subject.keywordAuthor | interconnect capacitance | - |
dc.subject.keywordAuthor | multilayer | - |
dc.subject.keywordAuthor | shielding effect | - |
dc.subject.keywordAuthor | signal delay | - |
dc.subject.keywordAuthor | VLSI interconnects | - |
dc.identifier.url | https://ieeexplore.ieee.org/document/929579 | - |
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