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A single event upset tolerant latch design
- Authors
- Wang, Haibin; Dai, Xixi; Wang, Yangsheng; Nofal, Issam; Cai, Li; Shen, Zicai; Sun, Wanxiu; Bi, Jinshun; Li, Bo; Guo, Gang; Chen, Li; Baeg, Sang
- Issue Date
- Sep-2018
- Publisher
- PERGAMON-ELSEVIER SCIENCE LTD
- Keywords
- Single event upset; Latch; DICE; Charge sharing; Radiation effects
- Citation
- MICROELECTRONICS RELIABILITY, v.88-90, pp 909 - 913
- Pages
- 5
- Indexed
- SCI
SCIE
SCOPUS
- Journal Title
- MICROELECTRONICS RELIABILITY
- Volume
- 88-90
- Start Page
- 909
- End Page
- 913
- ISSN
- 0026-2714
- Abstract
- This paper presents a single-event-upset tolerant latch design based on a redundant structure featuring four storage nodes (i.e. Quatro). The reference structure manifests single node upset issues when either of the two internal nodes is hit and observes a positive transient afterwards. Two OFF-state transistors are added to those two internal pull-up paths, suppressing positive transient. Simulation and experimental data demonstrate that the proposed design has smaller cross section and higher upset threshold than the reference design.
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Related Researcher
- Baeg, Sanghyeon
- ERICA 공학대학 (SCHOOL OF ELECTRICAL ENGINEERING)