Failure signature analysis of power-opens in DDR3 SDRAMs
- Authors
- Li, Tan; Lee, Hosung; Bak, Geunyong; Baeg, Sanghyeon
- Issue Date
- Sep-2018
- Publisher
- PERGAMON-ELSEVIER SCIENCE LTD
- Keywords
- Power pin; Open defect; Power integrity; VDD bounce; Power distribution
- Citation
- MICROELECTRONICS RELIABILITY, v.88-90, pp.277 - 281
- Indexed
- SCIE
SCOPUS
- Journal Title
- MICROELECTRONICS RELIABILITY
- Volume
- 88-90
- Start Page
- 277
- End Page
- 281
- URI
- https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/5662
- DOI
- 10.1016/j.microrel.2018.06.104
- ISSN
- 0026-2714
- Abstract
- Open defects in power pins can only be diagnosed indirectly, and these diagnoses are a challenging task in failure analysis due to the failure signature's aliasing to other issues. Open defects cannot be detected by traditional DC type test methods and can remain a potential risk in stressful device operation. In this work, error signatures in power open faults are experimentally probed to better understand electrical signatures induced by power-open. The power open faults are intentionally injected into a DDR3 SDRAM test platform. The power network inside the DDR3 SDRAM is experimentally found to be asymmetrical. Power-open defects in one power pin produce a range of power noise (0-65 mV), depending on the location of the power pin.
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