Split구조기반 자가보정 파이프라인 ADC

Abstract

Chip makers suffer from the performance degradation of pipelined ADCs, due to the capacitance mismatch issue from their manufacturing process. This work proposes an efficient digitally calibrated pipelined ADC architecture, based on Jacobi iteration method along with the split configuration. The simulation results showed the significant improvements such as 5dB increase of SNR and 0.6 LSB decrease of DNL. The proposed method can thus be used as a practical calibration architecture for commercial ADCs.