Cost-efficient Chip Identification Method using Scan Flip-flop based Physically Unclonable Function
- Authors
- Kim, Dooyoung; Ansari, M. Adil; Jung, Jihun; Kim, Jinuk; Park, Sungju
- Issue Date
- Apr-2018
- Publisher
- IEEK PUBLICATION CENTER
- Keywords
- Bayesian theorem; counterfeit ICs; hardware security; physically unclonable function; scan design
- Citation
- JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, v.18, no.2, pp.218 - 226
- Indexed
- SCIE
SCOPUS
KCI
- Journal Title
- JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
- Volume
- 18
- Number
- 2
- Start Page
- 218
- End Page
- 226
- URI
- https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/6372
- DOI
- 10.5573/JSTS.2018.18.2.218
- ISSN
- 1598-1657
- Abstract
- Scan flip-flop based physically unclonable function (SCAN-PUF) has been proposed to protect integrated circuits (ICs) from security threats such as unauthorized access and IC cloning. In this paper, we propose an efficient SCAN-PUF technique that improves the uniqueness of responses with low cost overhead. The proposed SCAN-PUF first determines an optimal number of power-up state observations and then selects scan flip-flops as the PUF elements (P-ELEMENTs) through a given number of observations. A Bayesian model is adopted to evaluate the reliability of the P-ELEMENTs, and a grouped P-ELEMENT selection method is introduced to obtain more P-ELEMENTs than a predetermined threshold. To evaluate the proposed SCAN-PUF, we observed the power-up states of scan flip-flops from 15 chips fabricated using the 65-nm CMOS technology. The optimal number of observations is determined according to the reliability of the P-ELEMENTs, and the reliability, randomness, and uniqueness of the responses are then analyzed.
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