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A Quatro-Based 65-nm Flip-Flop Circuit for Soft-Error Resilience
- Authors
- Li, Y. -Q.; Wang, H. -B.; Liu, R.; Chen, L.; Nofal, I.; Shi, S. -T.; He, A. -L; Guo, G.; Baeg, S. H.; Wen, S. -J.; Wong, R.; Chen, M.; Wu, Q.
- Issue Date
- Jun-2017
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Keywords
- Flip-Flop; Quatro; radiation hardness by design (RHBD); soft error
- Citation
- IEEE TRANSACTIONS ON NUCLEAR SCIENCE, v.64, no.6, pp 1554 - 1561
- Pages
- 8
- Indexed
- SCI
SCIE
SCOPUS
- Journal Title
- IEEE TRANSACTIONS ON NUCLEAR SCIENCE
- Volume
- 64
- Number
- 6
- Start Page
- 1554
- End Page
- 1561
- ISSN
- 0018-9499
1558-1578
- Abstract
- A flip-flop circuit hardened against soft errors is presented in this paper. This design is an improved version of Quatro for further enhanced soft-error resilience by integrating the guard-gate technique. The proposed design, as well as reference Quatro and regular flip-flops, was implemented and manufactured in a 65-nm CMOS bulk technology. Experimental characterization results of their alpha and heavy ions soft-error rates verified the superior hardening performance of the proposed design over the other two circuits.
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Related Researcher
- Baeg, Sanghyeon
- ERICA 공학대학 (SCHOOL OF ELECTRICAL ENGINEERING)