Short-Channel Tunneling Field-Effect Transistor with Drain-Overlap and Dual-Metal Gate Structure for Low-Power and High-Speed Operations

Abstract

We have investigated and proposed a highly scaled tunneling field-effect transistor (TFET) based on Ge/GaAs heterojunction with a drain overlap to suppress drain-induced barrier thinning (DIBT) and improve low-power (LP) performance. The highly scaled TFET with a drain overlap achieves lower leakage tunneling current because of the decrease in tunneling events between the source and drain, whereas a typical short-channel TFET suffers from a great deal of tunneling leakage current due to the DIBT at the off-state. However, the drain overlap inevitably increases the gate-to-drain capacitance (C-gd) because of the increase in the overlap capacitance (C-ov) and inversion capacitance (C-inv). Thus, in this work, a dual-metal gate structure is additionally applied along with the drain overlap. The current performance and the total gate capacitance (C-gg) of the device with a dual-metal gate can be possibly controlled by adjusting the metal gate workfunction (phi(gate)) and phi(overlap-gate) in the overlapping regions. As a result, the intrinsic delay time (tau) is greatly reduced by obtaining lower C-gg divided by the on-state current (I-on), i.e., C-gg/I-on. We have successfully demonstrated excellent LP and high-speed performance of a highly scaled TFET by adopting both drain overlap and dual-metal gate with DIBT minimization.