A polycrystalline-silicon dual-gate MOSFET-based 1T-DRAM using grain boundary-induced variable resistance

Abstract

A polycrystalline-silicon (poly-Si) dual-gate MOSFET-based one-transistor dynamic random-access memory (1T-DRAM) cell was developed using grain boundary (GB)-induced barrier effects. The program/erase operation of the 1T-DRAM is performed by trapping/detrapping charges in GB traps. The trapped charges cause variations in the grain energy barrier of the storage region, which forms the sensing margin of the 1T-DRAM. The proposed cell achieved a high sensing margin of 4.45 mu A/mu m and a long retention time (>100 ms) at a high temperature of 373 K (100 degrees C). Published under license by AIP Publishing.