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A Band-Engineered One-Transistor DRAM With Improved Data Retention and Power Efficiency
- Issue Date
- Apr-2019
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Keywords
- One-transistor DRAM; SiGe quantum well; band-to-band tunneling; DRAM retention; low-power operation
- Citation
- IEEE ELECTRON DEVICE LETTERS, v.40, no.4, pp.562 - 565
- Journal Title
- IEEE ELECTRON DEVICE LETTERS
- Volume
- 40
- Number
- 4
- Start Page
- 562
- End Page
- 565
- ISSN
- 0741-3106
- Abstract
- In this letter, a one-transistor (1T) dynamic random-access memory (DRAM) with SiGe quantum well (QW) is proposed, and its performance is validated through the technology computer-aided design (TCAD) simulation. At the write operation, band-to-band tunneling is used and 1 V or lower programming voltage is realized by inserting the SiGe QW beside the drain. This QW also functions as the storage node, which enhances not only the current sensing margin but also the retention time (tau(ret)) compared with those of all-Si device. At an extremely scaled cell size and sub-10-ns write/erase operations, the proposed device shows 0.2-s-long tau(ret) and current ratio > 10(4). It has been verified that a single cycle of 1T DRAM operations consumes only 93.8 fJ.
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Related Researcher
- Cho, Seong Jae
- IT (Major of Electronic Engineering)