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Analysis of the sensing margin of silicon and poly-Si 1T-DRAM

Authors
Kim H.Yoo S.Kang I.-M.Cho S.Sun W.Shin H.
Issue Date
Feb-2020
Publisher
MDPI AG
Keywords
Electron trapping; Grain boundary; One-transistor dynamic random-access memory (1T-DRAM); Polysilicon
Citation
Micromachines, v.11, no.2, pp.1 - 8
Journal Title
Micromachines
Volume
11
Number
2
Start Page
1
End Page
8
URI
https://scholarworks.bwise.kr/gachon/handle/2020.sw.gachon/26374
DOI
10.3390/mi11020228
ISSN
2072-666X
Abstract
Recently, one-transistor dynamic random-access memory (1T-DRAM) cells having a polysilicon body (poly-Si 1T-DRAM) have attracted attention as candidates to replace conventional one-transistor one-capacitor dynamic random-access memory (1T-1C DRAM). Poly-Si 1T-DRAM enables the cost-effective implementation of a silicon-on-insulator (SOI) structure and a three-dimensional (3D) stacked architecture for increasing integration density. However, studies on the transient characteristics of poly-Si 1T-DRAM are still lacking. In this paper, with TCAD simulation, we examine the differences between the memory mechanisms in poly-Si and silicon body 1T-DRAM. A silicon 1T-DRAM cell's data state is determined by the number of holes stored in a floating body (FB), while a poly-Si 1T-DRAM cell's state depends on the number of electrons trapped in its grain boundary (GB). This means that a poly-Si 1T-DRAM can perform memory operations by using GB as a storage region in thin body devices with a small FB area. © 2020 by the authors.
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