Characterization and Optimization of Inverted-T FinFET Under Nanoscale Dimensions
- Authors
- Yu, Eunseon; Heo, Keun; Cho, Seongjae
- Issue Date
- Aug-2018
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Keywords
- 3-D technology computer-aided design (TCAD) simulation; high current drive; high performance (HP); intrinsic gate delay; inverted-T FinFET (IT FinFET); low power operation; short-channel effects (SCEs); silicon-on-insulator (SOI) FinFET; wavy FinFET
- Citation
- IEEE TRANSACTIONS ON ELECTRON DEVICES, v.65, no.8, pp.3521 - 3527
- Journal Title
- IEEE TRANSACTIONS ON ELECTRON DEVICES
- Volume
- 65
- Number
- 8
- Start Page
- 3521
- End Page
- 3527
- URI
- https://scholarworks.bwise.kr/gachon/handle/2020.sw.gachon/3496
- DOI
- 10.1109/TED.2018.2846478
- ISSN
- 0018-9383
- Abstract
- In this paper, a p-type inverted-T FinFET (IT FinFET) has been optimally structured. Focus is made on analyzing the inferior characteristics reported from the previously fabricated IT FinFETs, and obtaining better performances through a novel structure. IT FinFET has a higher layout efficiency and can thus provide larger drain current (I-D) under the same dimension as that of a silicon-oninsulator (SOI) FinFET by securing the extended channels of ultrathin body (UTB) on the field region. We closely observe the leverages of fin width (W-fin), UTB height (H-UTB), and gate length (L-g) on the operation characteristics using a 3-D technology computer-aided design simulation with quantum-mechanicalmodels. Wfin below 10 nmis evaluated to be suitable for strong gate controllability. We first examine a critical H-UTB, beyond which a higher drive current is not obtained even with a greater channel width than that of FinFET. When H-UTB = 3 and 10 nm, IT FinFET yields 13.3% and 142% of saturation current improvement compared with SOI FinFET under the same footprint. At extremely scaled Lg, although the immunity against short-channel effects is slightly weaker than that of SOI FinFET, optimally designed IT FinFET can produce a higher current and demonstrates shorter intrinsic delay times.
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