Core-Shell Dual-Gate Nanowire Charge-Trap Memory for Synaptic Operations for Neuromorphic Applications
- Authors
- Ansari, M.H.R.; Kannan, U.M.; Cho, Seongjae
- Issue Date
- Jul-2021
- Publisher
- MDPI
- Keywords
- Band-to-band tunneling; Charge-trap synaptic transistor; Long-term potentiation (LTP); Neural network; Neuromorphic system; Pattern recognition; Short-term potentiation (STP)
- Citation
- Nanomaterials, v.11, no.7
- Journal Title
- Nanomaterials
- Volume
- 11
- Number
- 7
- URI
- https://scholarworks.bwise.kr/gachon/handle/2020.sw.gachon/81800
- DOI
- 10.3390/nano11071773
- ISSN
- 2079-4991
- Abstract
- This work showcases the physical insights of a core-shell dual-gate (CSDG) nanowire transistor as an artificial synaptic device with short/long-term potentiation and long-term depres-sion (LTD) operation. Short-term potentiation (STP) is a temporary potentiation of a neural net-work, and it can be transformed into long-term potentiation (LTP) through repetitive stimulus. In this work, floating body effects and charge trapping are utilized to show the transition from STP to LTP while de-trapping the holes from the nitride layer shows the LTD operation. Furthermore, linearity and symmetry in conductance are achieved through optimal device design and biases. In a system-level simulation, with CSDG nanowire transistor a recognition accuracy of up to 92.28% is obtained in the Modified National Institute of Standards and Technology (MNIST) pattern recognition task. Complementary metal-oxide-semiconductor (CMOS) compatibility and high recognition accuracy makes the CSDG nanowire transistor a promising candidate for the implementation of neuromorphic hardware. © 2021 by the authors. Licensee MDPI, Basel, Switzerland.
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