Effects of dual-spacer dielectrics on low-power and high-speed performance of sub-10 nm tunneling field-effect transistors

Abstract

In this paper, we propose and investigate a dual-spacer dielectric structure for realizing a sub-10 nm tunneling field-effect transistors (TFET) with excellent low-power (LP) and switching performance. The effects of the dual-spacer dielectric were assessed by analyzing the direct current (DC) and radio frequency (RF) performance of the GaAs0.5Sb0.5/In0.53Ga0.47As heterojunction-based short channel TFETs. The dual-spacer dielectric that consists of hafnium oxide (HfO2) and silicon dioxide (SiO2) raises an energy-band on drain-side because of the fringe field induced by the high-k spacer dielectric HfO2. The raised energy-band suppresses direct band-to-band tunneling (BBT) through the channel region and drain-induced barrier thinning (DIBT) phenomenon with improvement in the off-state current (I-off) and subthreshold swing (S). The dual-spacer dielectric also influences total gate capacitance (C-gg) because the HfO2 in the dual-spacer dielectric increases out-fringe capacitance (C-of) in gate-to-drain capacitance (C-gd). Although the proposed TFET has a high C-gd, the optimized TFET with the HfO2 length (Ldual-spacer) of 30 nm achieves a lower intrinsic delay time (t), a higher cut-off frequency (f(T)), and a higher maximum oscillation frequency (f(max)) owing to higher current performance and smaller gate-to-source capacitance (C-gs). (C) 2016 The Japan Society of Applied Physics