Novel Process Technologies of a Deep-submicron MOSFET for the High Packing Density of Circuits

Abstract

We have presented some novel process ideas to solve the major challenging problems in submicron device techniques. The key ideas are the ultra-shallow LDD (lightly doped source/drain) junction formation by using the SPD (solid phase diffusion) through ‘amorphous Si / thin oxide’ layer and the Ti silicidation by using selectively etched a-Si layer which is extended over the field oxide region. This TiSi2 layer could be used as a local interconnect with the shrinkage of physical design width of the active mask. Using this FESD (Field Extended Source Drain) technology, the width of the physical active mask could be reduced 2.75 times smaller than that of the conventional structure. We have verified this technology successfully by the fabrication of PMOSFET with 0.76 m gate length.