A 40-nm CMOS 7-b 32-GS/s SAR ADC With Background Channel Mismatch Calibration

Abstract

This brief presents a 7-b 32-GS/s successive approximation register analog-to-digital converter (ADC) using a massive time-interleaving (TI) architecture. For low-skew multi-phase clocks, generation utilizing a delay-locked loop (DLL) phase-detector (PD) with a reduced offset is proposed to minimize skew between the clocks. Different clock path delays caused by distributed sub-ADCs over a large area in a massive TI-ADC are compensated for by multiplexing master clocks from the DLL. Offsets and skews in the sub-channels are calibrated on chip in the background via an additional dedicated sub-channel. A prototype chip was implemented in a 40-nm CMOS process with an active area of 0.36 mm(2). The measured SFDR and SNDR of the prototype ADC at a conversion rate of 32 GS/s are 43.1 and 31.4 dB, respectively. The ADC, including the input buffers, consumes 125 mW under a single 0.9-V supply.