A 65-nm CMOS 6-Bit 20 GS/s Time-Interleaved DAC With Full-Binary Sub-DACs
- Authors
- Kim, Si-Nai; Kim, Woo-Cheol; Seo, Min-Jae; Ryu, Seung-Tak
- Issue Date
- Sep-2018
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Keywords
- DAC; time-interleaving; high-speed interface
- Citation
- IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.65, no.9, pp.1154 - 1158
- Journal Title
- IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
- Volume
- 65
- Number
- 9
- Start Page
- 1154
- End Page
- 1158
- URI
- https://scholarworks.bwise.kr/gachon/handle/2020.sw.gachon/83654
- DOI
- 10.1109/TCSII.2018.2809965
- ISSN
- 1549-7747
- Abstract
- A 6-bit 20 GS/s two-channel time-interleaved current-steering digital-to-analog converter (DAC) with compact full-binary sub-DACs is presented. Optimally adjusted transition timings between the input data and the interleaving clock minimize glitches by the time-interleaving switches and enhance the high-frequency linearity. In order to prevent static linearity degradation by the leakage current through the time-interleaving switches, the relationship between the output current and the leakage current is analyzed. The proposed DAC architecture and the pseudo-differential logic gates for the high-speed data interface reduce the circuit complexity as well as the power consumption. The prototype 6-bit 20 GS/s DAC, fabricated in a 65-nm CMOS process, achieves a spurious-free dynamic range of 35.1 dB up to the Nyquist input, and consumes 136 mW given a 1.2-V power supply.
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