Normalized-Full-Scale-Referencing Digital-Domain Linearity Calibration for SAR ADC
- Authors
- Chang, Dong-Jin; Kim, Wan; Seo, Min-Jae; Hong, Hyeok-Ki; Ryu, Seung-Tak
- Issue Date
- Feb-2017
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Keywords
- Capacitor DAC; CDAC linearity calibration; digital calibration; full-scale referring calibration; SAR ADC; time-interleaved ADC.
- Citation
- IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.64, no.2, pp.322 - 332
- Journal Title
- IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
- Volume
- 64
- Number
- 2
- Start Page
- 322
- End Page
- 332
- URI
- https://scholarworks.bwise.kr/gachon/handle/2020.sw.gachon/83658
- DOI
- 10.1109/TCSI.2016.2612692
- ISSN
- 1549-8328
- Abstract
- This paper proposes a linearity calibration algorithm of a capacitive digital-to-analog converter (CDAC) for successive approximation register (SAR) analog-to-digital converters (ADCs) based on a normalized-full-scale of the DAC. Since the capacitor weight errors are represented as the difference between the real and ideal weights with respect to the normalized-full-scale, the calibrated digital representation of CDAC does not have gain error. A model of a 14-bit-format SAR ADC with a segmented CDAC by a bridge capacitor is simulated to demonstrate the performance of the proposed calibration algorithm. The effective number of bits (ENOB) and spurious-free dynamic range (SFDR) of the 14-bit-format ADC model are improved to 13.2 bits and 94.0 dB from 8.4 bits and 54.8 dB, respectively, at a standard deviation of a unit capacitor of 2%. The gain-error-free characteristic of the proposed linearity calibration algorithm is verified with a 2-channel time-interleaved (TI) SAR ADC model.
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