A 0.6 V 12 b 10 MS/s Low-Noise Asynchronous SAR-Assisted Time-Interleaved SAR (SATI- SAR) ADC
- Authors
- Kim, Wan; Hong, Hyeok-Ki; Roh, Yi-Ju; Kang, Hyun-Wook; Hwang, Sun-Il; Jo, Dong-Shin; Chang, Dong-Jin; Seo, Min-Jae; Ryu, Seung-Tak
- Issue Date
- Aug-2016
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Keywords
- Asynchronous SAR ADC; gain-boosting dynamic comparator; low voltage; low-jitter clock; low-noise comparator; SAR-assisted time-interleaved SAR (SATI-SAR)
- Citation
- IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.51, no.8, pp.1826 - 1839
- Journal Title
- IEEE JOURNAL OF SOLID-STATE CIRCUITS
- Volume
- 51
- Number
- 8
- Start Page
- 1826
- End Page
- 1839
- URI
- https://scholarworks.bwise.kr/gachon/handle/2020.sw.gachon/83659
- DOI
- 10.1109/JSSC.2016.2563780
- ISSN
- 0018-9200
- Abstract
- This paper presents an asynchronous SAR-assisted time-interleaved SAR (SATI-SAR) ADC as a suitable architecture in a low-supply-voltage condition. Settling-While-Conversion enabled by the Assist-ADC relaxes the DAC settling time requirement and makes it possible to insert a minimized capacitor shuffling logic with no speed penalty. A proposed gain-boosting dynamic pre-amplifier enhances the noise performance of the comparator and a self time-reference generation function is embedded in the pre-amplifier for a speed-enhanced asynchronous decision. A proposed dual-mode clock generator generates a low-jitter fixed-width sampling pulse for high-frequency operation while it generates a low-power-but-low-quality clock for low-frequency operation. With the dual-mode clock generator enabled, a prototype 65 nm CMOS 0.6 V 12 b 10 MS/s ADC achieves an ENOB of 10.4 at a Nyquist-rate input, and the peaks of DNL and INL are measured to be 0.24 LSB and 0.45 LSB, respectively. The FoM is 6.2 fJ/conversion-step with a power consumption of 83 mu W. The ADC operates under the lowest supply voltage of 0.6 V among comparable designs with ENOBs over 10 and conversion rates over 1 MS/s.
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