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1T DRAM with Raised SiGe Quantum Well for Sensing Margin Improvement
- Authors
- Lee, Si-Won; Cho, Seongjae; Cho, Il Hwan; Kim, Garam
- Issue Date
- Feb-2023
- Publisher
- 대한전자공학회
- Keywords
- One-transistor (1T) dynamic random-access memory (DRAM); sensing margin; technology computer-aided design (TCAD)
- Citation
- JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, v.23, no.1, pp.64 - 70
- Journal Title
- JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
- Volume
- 23
- Number
- 1
- Start Page
- 64
- End Page
- 70
- ISSN
- 1598-1657
- Abstract
- In this paper, a novel one-transistor dynamic random-access memory (1T DRAM) with a raised SiGe quantum well (QW) under one gate in the double-gate (DG) structure is proposed. The proposed structure can improve the poor performance of the retention time and sensing margin which is the problem of the conventional 1T DRAM. In write operation, the performance is improved through the band to band tunneling (BTBT) between body and drain and through valence band offset between SiGe and Si. Also by utilizing the physical barrier of oxide, read “1” retention time can be increased. The fabrication process is also proposed.
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Related Researcher
- Cho, Seong Jae
- IT (Major of Electronic Engineering)