A reconfigurable binary/ternary logic conversion-in-memory based on drain-aligned floating-gate heterojunction transistorsopen access
- Authors
- Lee, Chungryeol; Lee, Changhyeon; Lee, Seungmin; Choi, Junhwan; Yoo, Hocheon; Im, Sung Gap
- Issue Date
- Jun-2023
- Publisher
- NATURE PORTFOLIO
- Citation
- NATURE COMMUNICATIONS, v.14, no.1
- Journal Title
- NATURE COMMUNICATIONS
- Volume
- 14
- Number
- 1
- URI
- https://scholarworks.bwise.kr/gachon/handle/2020.sw.gachon/88748
- DOI
- 10.1038/s41467-023-39394-5
- ISSN
- 2041-1723
- Abstract
- A new type of heterojunction non-volatile memory transistor (H-MTR) has been developed, in which the negative transconductance (NTC) characteristics can be controlled systematically by a drain-aligned floating gate. In the H-MTR, a reliable transition between N-shaped transfer curves with distinct NTC and monolithically current-increasing transfer curves without apparent NTC can be accomplished through programming operation. Based on the H-MTR, a binary/ternary reconfigurable logic inverter (R-inverter) has been successfully implemented, which showed an unprecedentedly high static noise margin of 85% for binary logic operation and 59% for ternary logic operation, as well as long-term stability and outstanding cycle endurance. Furthermore, a ternary/binary dynamic logic conversion-in-memory has been demonstrated using a serially-connected R-inverter chain. The ternary/binary dynamic logic conversion-in-memory could generate three different output logic sequences for the same input signal in three logic levels, which is a new logic computing method that has never been presented before. Reconfigurable logic is desirable for high-density information processing. Here, the authors demonstrate a binary/ternary logic conversion-in-memory, which can operate in both binary and ternary logic systems to implement various types of logic gates.
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