Reducing Refresh Overhead with In-DRAM Error Correction Codes

Abstract

DRAM technology scaling has continuously improved memory density, but the limited cell capacitance makes more susceptible to reliability issues. Hence, it has become inevitable to employ in-DRAM ECC. Also, the performance and power consumption overhead due to refresh operations have become a critical issue as the DRAM density increases. Therefore, it is very important to reduce the refresh overhead without sacrificing the reliability of DRAM. In this paper, we propose a retention-Aware refresh scheme with in-DRAM ECC. The key idea of our proposed method is that the in-DRAM ECC can correct a single-bit error, and this will effectively reduce the number of weak rows that have to be refreshed every 64ms. Also, a runtime profiler is proposed to keep up-To-date information of weak rows to solve the variable retention time problem. Our experiments with SPEC benchmarks show up to 6.8% performance improvement of performance, and up to 15.4% reduction of power consumption compared with the conventional refresh schemes.