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High-speed StrongARM-latch-based Bang-bang Phase Detector in 40-nm CMOS Technology
- Authors
- Sung, Gaeryun; Han, Jae duk
- Issue Date
- Nov-2021
- Publisher
- IEEE
- Keywords
- clock-To-Q delay; phase detector; power consumption; StorngARM latch
- Citation
- Proceedings - International SoC Design Conference 2021, ISOCC 2021, pp.377 - 378
- Indexed
- SCOPUS
- Journal Title
- Proceedings - International SoC Design Conference 2021, ISOCC 2021
- Start Page
- 377
- End Page
- 378
- ISSN
- 2163-9612
- Abstract
- This paper presents a high-speed strongARM-latch-based bang-bang phase detector (PD). Instead of using D-flipflops (DFF) or D-latches, which are used in conventional bang-bang PDs, strongARM latches are used to achieve high sensitivity owing to their regeneration behaviors. By comparing the clock-To-Q delay(tcq) and maximum data rate of conventional and proposed phase detectors, it is found that the proposed strongARM-latch-based bang-bang PD has a smaller clock-To-Q delay and a higher data rate.
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Related Researcher
- Han, Jaeduk
- COLLEGE OF ENGINEERING (SCHOOL OF ELECTRONIC ENGINEERING)