Solution-processed n-type fullerene field-effect transistors prepared using CVD-grown graphene electrodes: improving performance with thermal annealingopen access
- Authors
- Jeong, Yong Jin; Yun, Dong-Jin; Jang, Jaeyoung; Park, Seonuk; An, Tae Kyu; Kim, Lae Ho; Kim, Se Hyun); Park, Chan Eon
- Issue Date
- Mar-2015
- Publisher
- ROYAL SOC CHEMISTRY
- Citation
- PHYSICAL CHEMISTRY CHEMICAL PHYSICS, v.17, no.9, pp.6635 - 6643
- Indexed
- SCIE
SCOPUS
- Journal Title
- PHYSICAL CHEMISTRY CHEMICAL PHYSICS
- Volume
- 17
- Number
- 9
- Start Page
- 6635
- End Page
- 6643
- URI
- https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/157648
- DOI
- 10.1039/c4cp05787b
- ISSN
- 1463-9076
- Abstract
- Solution-processed organic field effect transistors (OFETs), which are amenable to facile large-area processing methods, have generated significant interest as key elements for use in all-organic electronic applications aimed at realizing low-cost, lightweight, and flexible devices. The low performance levels of n-type solution-processed bottom-contact OFETs unfortunately continue to pose a barrier to their commercialization. In this study, we introduced a combination of CVD-grown graphene source/drain (S/D) electrodes and fullerene (C-60) in a solution-processable n-type semiconductor toward the fabrication of n-type bottom-contact OFETs. The C-60 coating in the channel region was achieved by modifying the surface of the oxide gate dielectric layer with a phenyl group-terminated self-assembled monolayer (SAM). The graphene and phenyl group in the SAMs induced pi-pi interactions with C-60, which facilitated the formation of a C-60 coating. We also investigated the effects of thermal annealing on the reorganization properties and field-effect performances of the overlaying solution-processed C-60 semiconductors. We found that thermal annealing of the C-60 layer on the graphene surface improved the crystallinity of the face-centered cubic (fcc) phase structure, which improved the OFET performance and yielded mobilities of 0.055 cm(2) V-1 s(-1). This approach enables the realization of solution-processed C-60-based FETs using CVD-grown graphene S/D electrodes via inexpensive and solution-process techniques.
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