Zero bit error rate ID generation circuit using via formation probability in 0.18 mu m CMOS process
- Authors
- Kim, Tae-Won; Choi, Byong-Deok; Kim, Dong Kyue
- Issue Date
- Jun-2014
- Publisher
- INST ENGINEERING TECHNOLOGY-IET
- Citation
- ELECTRONICS LETTERS, v.50, no.12, pp.876 - 877
- Indexed
- SCIE
SCOPUS
- Journal Title
- ELECTRONICS LETTERS
- Volume
- 50
- Number
- 12
- Start Page
- 876
- End Page
- 877
- URI
- https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/159863
- DOI
- 10.1049/el.2013.3474
- ISSN
- 0013-5194
- Abstract
- An integrated circuit for a physical unclonable function (PUF) to generate an identifier for each device is proposed based on the via formation probability. The via hole size is determined to be smaller than that specified by the design rule which guarantees successful via formation. As a result, a via is formed with a certain probability. A proper via hole size and a post-processing method are found to obtain very high randomness in the bit sequences, and it is confirmed that the bit error rate is zero through repeated measurements over one year under the supply voltage variations with noises and in a wide range of temperature. This time invariance of bits can be attributed to the fact that the via formation does not change over time, once they are formed.
- Files in This Item
-
Go to Link
- Appears in
Collections - 서울 공과대학 > 서울 융합전자공학부 > 1. Journal Articles
![qrcode](https://api.qrserver.com/v1/create-qr-code/?size=55x55&data=https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/159863)
Items in ScholarWorks are protected by copyright, with all rights reserved, unless otherwise indicated.