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An efficient check node operation circuit for Min-Sum based LDPC decoder
- Authors
- Cho, Keol; Chung, Ki-Seok
- Issue Date
- Apr-2014
- Publisher
- Institute of Electrical and Electronics Engineers Inc.
- Keywords
- circuit size; LDPC decoder; low power; low-density parity-check codes
- Citation
- Proceedings of the International Symposium on Consumer Electronics, ISCE, pp.1 - 2
- Indexed
- SCOPUS
- Journal Title
- Proceedings of the International Symposium on Consumer Electronics, ISCE
- Start Page
- 1
- End Page
- 2
- ISSN
- 0000-0000
- Abstract
- This paper presents a low power and area-efficient check node operation circuit for LDPC decoders based on Min-Sum algorithm. By improving a heavily used comparator circuit, our proposed check node unit reduces area and power consumption by 8% and 13%, respectively, without decoding speed degradation compared to conventional LDPC decoders.
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Related Researcher
- Chung, Ki Seok
- COLLEGE OF ENGINEERING (SCHOOL OF ELECTRONIC ENGINEERING)