A test method for power management of SoC-based microprocessors

Abstract

Power management in system-on-chip (SoC) has become one of the most crucial techniques for mobile devices. Among many intellectual properties (IP) of SoC, a microprocessor, which is one of the major power consumers in the system, is a key component in SoC power management. Controlling idle states for microprocessors, which is typically implemented by combinations of clock gating and power gating, needs a testing method at operating system level after pre-silicon verification. When a microprocessor performs power state transitions, the microprocessor's architectural state and the contents of local cache memory are corrupted. It cannot handle service requests from other peripheral IPs as well. Therefore, it is important to ensure that the system operates correctly with its original execution state after power state transitions. This paper addresses a testing methodology for power state switching of microprocessor at system level.