A multi-level capacitor-less memory cell fabricated on a nano-scale strained silicon-on-insulator
- Authors
- Park, Jea-Gun; Kim, Seong-Je; Shin, Mi-Hee; Song, Seung-Hyun; Chung, Sung-Woong; Enomoto, Hirofumi; Shim, Tae-Hun
- Issue Date
- Aug-2011
- Publisher
- IOP PUBLISHING LTD
- Citation
- NANOTECHNOLOGY, v.22, no.31, pp.1 - 7
- Indexed
- SCIE
SCOPUS
- Journal Title
- NANOTECHNOLOGY
- Volume
- 22
- Number
- 31
- Start Page
- 1
- End Page
- 7
- URI
- https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/167891
- DOI
- 10.1088/0957-4484/22/31/315201
- ISSN
- 0957-4484
- Abstract
- A multi-level capacitor-less memory cell was fabricated with a fully depleted n-metal-oxide-semiconductor field-effect transistor on a nano-scale strained silicon channel on insulator (FD sSOI n-MOSFET). The 0.73% biaxial tensile strain in the silicon channel of the FD sSOI n-MOSFET enhanced the effective electron mobility to similar to 1.7 times that with an unstrained silicon channel. This thereby enables both front-and back-gate cell operations, demonstrating eight-level volatile memory-cell operation with a 1 ms retention time and 12 mu A memory margin. This is a step toward achieving a terabit volatile memory cell.
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