Fabrication of microstructured silicon (mu s-Si) from a bulk Si wafer and its use in the printing of high-performance thin-film transistors on plastic substrates

Abstract

In this paper, we report a new fabrication route to generate microstructured, single-crystalline silicon (mu s-Si) ribbons using (1 1 0) silicon. Two different methods were explored for producing these printable structures. This work also introduces a second-process innovation in the fabrication of microstructured semiconductor objects for printed large-area circuits, namely the direct integration of a high-quality, thermally grown silicon dioxide (SiO2) layer for use as a gate dielectric in top-gate metal-oxide-silicon field effect transistors. We also demonstrate and characterize a soft, conformable lamination process that considerably enhances the mechanical stability of devices printed on plastic, allowing bending radii as small as 0.8 cm. These structures enable a reduction of the bending strains localized at the device interface. These improvements were fully characterized by finite element simulations of the strain distribution present in a descriptive model of the multilayer laminated circuit.