Optimal Channel Ion Implantation for High Memory Margin of Capacitor-Less Memory Cell Fabricated on Fully Depleted Silicon-on-Insulator
- Authors
- Kim, Seong-Je; Oh, Jung-Mi; Shim, Tae-Hun; Park, Jea-Gun
- Issue Date
- Mar-2010
- Publisher
- IOP PUBLISHING LTD
- Citation
- JAPANESE JOURNAL OF APPLIED PHYSICS, v.49, no.3, pp.1 - 4
- Indexed
- SCIE
SCOPUS
- Journal Title
- JAPANESE JOURNAL OF APPLIED PHYSICS
- Volume
- 49
- Number
- 3
- Start Page
- 1
- End Page
- 4
- URI
- https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/175315
- DOI
- 10.1143/JJAP.49.036507
- ISSN
- 0021-4922
- Abstract
- The effect of channel doping concentration on the memory margin of capacitor-less (Cap-less) memory cells fabricated on fully depleted silicononinsulator (SOI) n-metal-oxide- semiconductor field-effect transistors (MOSFETs) was investigated. It was observed that the memory margin of Cap-less memory cells is significantly varied by the channel doping concentration, i.e., it increases with doping concentrations up to 1.4 x 10(17) cm(-3) and then decreases with higher doping concentrations. In particular, at a concentration of 1.4 x 10(17) cm(-3) it increased 1.8 times compared with that at 1.5 x 10(15) cm(-3). This gives rise to speculation that the memory margin of Cap-less memory cells fabricated on fully depleted SOI n-MOSFETs can be increased by enlarging the lateral electric field and can be decreased by reducing the current density. These results suggest that a higher memory margin in Cap-less memory cells can be obtained by optimizing channel doping concentration in fully depleted SOI n-MOSFETs.
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