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Dual Gate ZnO-Based Thin-Film Transistors Operating at 5 V: NOR Gate Application

Authors
Park, Chung HoonLee, Kwang HongOh, Min SukLee, KimoonIm, SeongilLee, Byoung HunSung, Myung Mo
Issue Date
Jan-2009
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Keywords
Dual gate (DG); NOR logic gate; thin-film transistors (TFTs); ZnO
Citation
IEEE ELECTRON DEVICE LETTERS, v.30, no.1, pp.30 - 32
Indexed
SCIE
SCOPUS
Journal Title
IEEE ELECTRON DEVICE LETTERS
Volume
30
Number
1
Start Page
30
End Page
32
URI
https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/177414
DOI
10.1109/LED.2008.2007973
ISSN
0741-3106
Abstract
We report on the fabrication of ZnO-based dual gate (DG) thin-film transistors (TFTs) with 20-nm-thick Al2O3 for both top and bottom dielectrics, which were deposited by atomic layer deposition on glass substrates at 200 degrees C. As characterized with single gate (SG), DG, and ground plane (GP) modes, our ZnO TFTs are well operated under 5 V. DG-mode TFT showed a field mobility of 0.38 cm(2)/V.s, a high saturation current of 6 mu A, and an on/off current ratio of similar to 10(6), while SG- and GP-mode TFTs showed a similar value of mobility but with lower current. Using DG and GP modes, NOR gate operation was well demonstrated.
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