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Design of a Latchup-Free ESD Power Clamp for Smart Power ICsDesign of a Latchup-Free ESD Power Clamp for Smart Power ICs
- Other Titles
- Design of a Latchup-Free ESD Power Clamp for Smart Power ICs
- Issue Date
- Sep-2008
- Publisher
- 대한전자공학회
- Keywords
- Electrostatic discharge (ESD); darlington; power clamp; latchup; the lateral diffused MOS
- Citation
- JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, v.8, no.3, pp.227 - 231
- Indexed
- KCI
OTHER
- Journal Title
- JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
- Volume
- 8
- Number
- 3
- Start Page
- 227
- End Page
- 231
- ISSN
- 1598-1657
- Abstract
- A latchup-free design based on the lateral diffused MOS (LDMOS) adopting the "Darlington" approaches was designed. The use of Darlington configuration as the trigger circuit results in the reduction of the size of the circuit when compared to the conventional inverter driven RC-riggered MOSFET ESD power clamp circuits. The proposed clamp was fabricated using a 0.35 μm 60V BCD (Bipolar CMOS DMOS) process and the performance of the proposed clamp was successfully verified by TLP (Transmission Line Pulsing) measurements.
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Collections - 서울 공과대학 > 서울 융합전자공학부 > 1. Journal Articles
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Related Researcher
- Park, Sang Gyu
- COLLEGE OF ENGINEERING (SCHOOL OF ELECTRONIC ENGINEERING)