An Analysis of CMOS Latched Comparators
- Authors
- Yeom, Sunoh; 심태양; Han, Jaeduk
- Issue Date
- Feb-2023
- Publisher
- Institute of Electrical and Electronics Engineers Inc.
- Keywords
- clock-to-Q delay; CMOS; kickback noise; latched comparator; slicer
- Citation
- 2023 International Conference on Electronics, Information, and Communication, ICEIC 2023, pp 1 - 4
- Pages
- 4
- Indexed
- SCOPUS
- Journal Title
- 2023 International Conference on Electronics, Information, and Communication, ICEIC 2023
- Start Page
- 1
- End Page
- 4
- URI
- https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/184857
- DOI
- 10.1109/ICEIC57457.2023.10049873
- Abstract
- Using suitable types of CMOS latched comparators for specific conditions is vital -because each comparator has different pros and cons. Also, it is important to determine which comparators to utilize for specific conditions. A need remains for the practical comparison of various types of comparators with applicable criteria. Within the present study, we performed comparisons between StrongArm latch, modified double-tail latch, and track-and-regenerate slicer with three different types of criteria. We analyzed each comparator by controlling three types of variables: power supply, input common mode voltage, and differential signal input. Then, in keeping with these three types of criteria, the simulation results, kickback noise, power consumption, and clock-to-Q delay were evaluated. We designed three kinds of CMOS latched comparators with 40-nm CMOS technology. In post-layout simulations, using a StrongArm latch resulted in low power consumption. Modified double-tail latch showed strength in kickback noise and is applicable for low power supply. Track-and-regenerate slicer showed better performance in clock-to-Q delay. Our findings expand on the performance of each comparator that would be applied to mixed-signal circuits and systems.
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