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Dataflow에 따른 Systolic Array의 연산 성능 분석Analysis of Computing Performance of Systolic Arrays depending on Dataflows

Other Titles
Analysis of Computing Performance of Systolic Arrays depending on Dataflows
Authors
위대은박상수정기석
Issue Date
Nov-2022
Publisher
대한임베디드공학회
Keywords
Convolution neural network; Systolic array; Dataflow, Weight stationary; Output stationary; Compute cycles; etc.
Citation
2022 대한임베디드공학회 추계학술대회, v.0, no.0, pp.55 - 58
Indexed
OTHER
Journal Title
2022 대한임베디드공학회 추계학술대회
Volume
0
Number
0
Start Page
55
End Page
58
URI
https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/188561
Abstract
Today, Deep Neural Networks (DNNs) have been widely used for various applications. Because the DNNs require a large amount of computation, hardware accelerators are commonly used to speed up the inference processing. In the systolic array architecture, a common hardware structure for neural network accelerators, the type of dataflow defines how data is stored in a processing element (PE) and exchanged among adjacent PEs. The computing performance of the systolic array differs depending on the type of the dataflows. Therefore, data flow analysis is crucial to maximize the inference performance. In this work, the computing performance depending on the data flows is evaluated using an open-source systolic array simulator called SCALE-Sim, Experimental results show that the inference latency differs up to 3.2 times depending on the type of the dataflow.
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서울 공과대학 > 서울 융합전자공학부 > 1. Journal Articles

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Chung, Ki Seok
COLLEGE OF ENGINEERING (SCHOOL OF ELECTRONIC ENGINEERING)
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