Incremental drain-voltage-ramping training method for ferroelectric field-effect transistor synaptic devices
- Authors
- Nguyen, Manh-Cuong; Lee, Kitae; Kim, Sihyun; Youn, Sangwook; Hwang, Yeongjin; Kim, Hyungjin; Choi, Rino; Kwon, Daewoong
- Issue Date
- Jan-2022
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Keywords
- FeFETsTraining; Logic gates; Linearity; DepressionTransistors; Threshold voltage; Ferroelectric FET (FeFET); HZO; FeFET synaptic device; neuromorphic training method
- Citation
- IEEE ELECTRON DEVICE LETTERS, v.43, no.1, pp.17 - 20
- Indexed
- SCIE
SCOPUS
- Journal Title
- IEEE ELECTRON DEVICE LETTERS
- Volume
- 43
- Number
- 1
- Start Page
- 17
- End Page
- 20
- URI
- https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/188921
- DOI
- 10.1109/LED.2021.3127927
- ISSN
- 0741-3106
- Abstract
- We demonstrate a HfZrO2 (HZO) ferroelectric field-effect transistor fabricated on a silicon-on-insulator substrate, targeting MHz synaptic device applications. Stable multistate weights were implemented with robust retention, excellent linearity, and symmetric potentiation/depression (P/D) in the fabricated HZO ferroelectric field-effect transistors (FeFETs). To further improve the linearity and symmetry of the P/D and to expand the operating condition of the FeFETs as a synaptic device, a novel incremental drain-voltage-ramping method was proposed, and its compatibility was verified thoroughly. The results revealed that a linear and symmetric P/D with stable repeatability was obtained under a wide range of operating conditions, and a learning accuracy of 95% was achieved through MNIST pattern recognition simulations.
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