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Ferroelectric-Metal Field-Effect Transistor With Recessed Channel for 1T-DRAM Application

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dc.contributor.authorLee, Kitae-
dc.contributor.authorKim, Sihyun-
dc.contributor.authorLee, Jong-Ho-
dc.contributor.authorKwon, Daewoong-
dc.date.accessioned2023-08-07T07:48:19Z-
dc.date.available2023-08-07T07:48:19Z-
dc.date.created2023-07-21-
dc.date.issued2021-11-
dc.identifier.issn21686734-
dc.identifier.urihttps://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/188922-
dc.description.abstractThe ferroelectric-metal field-effect transistor with recessed channel (RC-FeMFET) is proposed for one transistor dynamic random-access memory (1T-DRAM). Through technology computer-aided design (TCAD) simulations, the effects of inter-metal insertion on the FeFET with recessed channel (RC-FeFET) is identified. By evaluating electric field (e-field) across interlayer (IL) and memory window (MW), the improvements of program/erase cycling endurance and read current sensing margin (RSM) are verified in the RC-FeMFET. Moreover, considering program voltage (V-W) and polarization switching time (tau(p)), the guide line of the RC-FeMFET design is provided in terms of e-field across IL and MW for 1T-DRAM applications.-
dc.language영어-
dc.language.isoen-
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC-
dc.titleFerroelectric-Metal Field-Effect Transistor With Recessed Channel for 1T-DRAM Application-
dc.typeArticle-
dc.contributor.affiliatedAuthorKwon, Daewoong-
dc.identifier.doi10.1109/JEDS.2021.3127955-
dc.identifier.scopusid2-s2.0-85125506108-
dc.identifier.wosid000756799300003-
dc.identifier.bibliographicCitationIEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY, v.10, pp.13 - 18-
dc.relation.isPartOfIEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY-
dc.citation.titleIEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY-
dc.citation.volume10-
dc.citation.startPage13-
dc.citation.endPage18-
dc.type.rimsART-
dc.type.docType정기학술지(Article(Perspective Article포함))-
dc.description.journalClass1-
dc.description.isOpenAccessY-
dc.description.journalRegisteredClassscie-
dc.description.journalRegisteredClassscopus-
dc.relation.journalResearchAreaEngineering-
dc.relation.journalWebOfScienceCategoryEngineering, Electrical & Electronic-
dc.subject.keywordPlusMEMORY-
dc.subject.keywordPlusMECHANISMS-
dc.subject.keywordAuthorFerroelectric-gate field-effect transistor (FeFET)-
dc.subject.keywordAuthorFerroelectric devicesone transistor dynamic random-access memory (1T-DRAM)-
dc.subject.keywordAuthorendurance characteristics of FeFET-
dc.subject.keywordAuthorrecess channel-
dc.identifier.urlhttps://ieeexplore.ieee.org/document/9614332-
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