Ferroelectric-Metal Field-Effect Transistor With Recessed Channel for 1T-DRAM Application
DC Field | Value | Language |
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dc.contributor.author | Lee, Kitae | - |
dc.contributor.author | Kim, Sihyun | - |
dc.contributor.author | Lee, Jong-Ho | - |
dc.contributor.author | Kwon, Daewoong | - |
dc.date.accessioned | 2023-08-07T07:48:19Z | - |
dc.date.available | 2023-08-07T07:48:19Z | - |
dc.date.created | 2023-07-21 | - |
dc.date.issued | 2021-11 | - |
dc.identifier.issn | 21686734 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/188922 | - |
dc.description.abstract | The ferroelectric-metal field-effect transistor with recessed channel (RC-FeMFET) is proposed for one transistor dynamic random-access memory (1T-DRAM). Through technology computer-aided design (TCAD) simulations, the effects of inter-metal insertion on the FeFET with recessed channel (RC-FeFET) is identified. By evaluating electric field (e-field) across interlayer (IL) and memory window (MW), the improvements of program/erase cycling endurance and read current sensing margin (RSM) are verified in the RC-FeMFET. Moreover, considering program voltage (V-W) and polarization switching time (tau(p)), the guide line of the RC-FeMFET design is provided in terms of e-field across IL and MW for 1T-DRAM applications. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | Ferroelectric-Metal Field-Effect Transistor With Recessed Channel for 1T-DRAM Application | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Kwon, Daewoong | - |
dc.identifier.doi | 10.1109/JEDS.2021.3127955 | - |
dc.identifier.scopusid | 2-s2.0-85125506108 | - |
dc.identifier.wosid | 000756799300003 | - |
dc.identifier.bibliographicCitation | IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY, v.10, pp.13 - 18 | - |
dc.relation.isPartOf | IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY | - |
dc.citation.title | IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY | - |
dc.citation.volume | 10 | - |
dc.citation.startPage | 13 | - |
dc.citation.endPage | 18 | - |
dc.type.rims | ART | - |
dc.type.docType | 정기학술지(Article(Perspective Article포함)) | - |
dc.description.journalClass | 1 | - |
dc.description.isOpenAccess | Y | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.subject.keywordPlus | MEMORY | - |
dc.subject.keywordPlus | MECHANISMS | - |
dc.subject.keywordAuthor | Ferroelectric-gate field-effect transistor (FeFET) | - |
dc.subject.keywordAuthor | Ferroelectric devicesone transistor dynamic random-access memory (1T-DRAM) | - |
dc.subject.keywordAuthor | endurance characteristics of FeFET | - |
dc.subject.keywordAuthor | recess channel | - |
dc.identifier.url | https://ieeexplore.ieee.org/document/9614332 | - |
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